1. Field of the Invention
The invention relates in general to automated design of integrated circuits, and more particularly, to verification of integrated circuit designs at different levels of abstraction.
2. Description of the Related Art
Modern circuit design has evolved into a specialized field often referred to as electronic design automation in which computers and computer aided design (CAD) techniques are used to automate the integrated circuit (IC) design process. An IC design process typically begins with an engineer producing a high level design specification in terms of input/output signals, functionality and performance characteristics of a hardware circuit to be fabricated. These characteristics are captured in a high level hardware language model. This model may be decomposed into a plurality of sub-models, each of which is transformed to lower level abstraction models at the Register Transfer Level (RTL) for example. In the course of this transformation process, design choices are made among many possible detailed implementations.
Verification that a detailed design implementation produced from a high level design specification meets the functional requirements of the original design specification is a major issue in IC design. Various techniques have been developed to verify that a detailed model meets functional requirements of the original design specification. One approach involves the use of a testbench that includes a reference model, stimulus generator and output checker. The test bench effectively wraps around the model under test (e.g. an RTL model). The stimulus generator drives the model with stimulus signals, and the output checker checks the correctness of output from the model under test in response to the stimulus signals. The reference model is a computer program which calculates the correct results given any legal set of inputs. The output checker produces an error report if the design implementation does not meet the design specification. Another approach involves the use of assertions, a statement that some given property is required to hold and a directive to a verification tool to verify that the property does hold. A property may be a collection of logical and temporal relationships between and among boolean expressions, sequential expressions and/or other properties, which together represent some portion of behavior of a system. Formal verification involves the application of complex algorithms to test for properties in a design implementation.
Development of a testbench can be a time consuming, tedious and error prone activity. As a result, one shortcoming with the development of a testbench is a degree of uncertainty as to whether an error report produced during verification is due to an error in the design implementation or due to an error in the testbench. Thus, there has been a need for improvements in the production of verification environments to test whether a detailed implementation satisfies original design requirements. The present invention meets this need.